MPC8540 datasheet(660/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-34

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.5.3.3.2 Transmit Status Register (TSTAT)

TSTAT, shown in Figure 14-19, is written by TSEC to convey DMA status information.

Table 14-17 describes the fields of the TSTAT register.

21–26

—

Reserved

RFC_PAUSE Receive flow control pause frame. Written by TSEC. This read-only status bit is set if a flow

control pause frame was received and the transmitter is paused for the duration defined in the

received pause frame. This bit automatically clears after the pause duration is complete.

0 Pause duration complete.

1 Pause duration in progress.

TFC_PAUSE

Transmit flow control pause frame. Use this bit to transmit a PAUSE frame. To transmit a flow

control pause frame, first set FIFO_PAUSE_CTRL[TFC_PAUSE_EN]. Next, set

MACCFG1[GTS]. If TFC_PAUSE is then set, the MAC stops transmission of data frames after

the current transmission completes. The GTSC interrupt in the IEVENT register is asserted.

With transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame with

the duration value obtained from the PTV register. The TXC interrupt occurs after sending the

control pause frame. Next, the MAC clears TFC_PAUSE and resumes transmitting data frames.

Note that if the transmitter is paused due to user assertion of GTS or reception of a PAUSE

frame, the MAC may still transmit a MAC control PAUSE frame.

0 No outstanding pause frame transmission request.

1 Pause frame transmission requested.

29–31

—

Reserved

THLT

0000

000

0000

000

0000

000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4104; TSEC2:0x2_5104

Figure 14-19. TSTAT Register Definition

Table 14-17. TSTAT Field Descriptions

Bits

Name

Description

THLT

Transmit halt

0 No hardware-initiated transmission halt.

1 TSEC transmission function halted. This bit is written by TSEC to inform the user that it is no longer

processing transmit frames and that the transmit DMA function is disabled by hardware. To re-start

the transmission function, the user must clear this bit by writing a one.

1–31

—

Reserved

Table 14-16. TCTRL Field Descriptions (continued)

Bits

Name

Description

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