MPC8540 datasheet(664/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-38

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-22 describes the fields of the TBASE register.

14.5.3.3.8 Out-of-Sequence TxBD Register (OSTBD)

The out-of-sequence TxBD register, OSTBD, shown in Figure 14-25, includes the status/control

and data length in the same format as a regular TxBD. It is useful for sending flow control frames.

OSTBD[R] is always checked between frames. If it is not ready, a regular frame is sent. If a flow

control frame is sent and OSTBD[I] is set, a TXC event is generated after frame transmission. This

area must be cleared while not in use. Once the TSEC is in paused mode the out-of-sequence buffer

descriptor cannot be used to send another flow control frame because the MAC regards it as a

regular TxBD.

28 29

TBASE

000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_4204; TSEC2:0x2_5204

Figure 14-24. TBASE Register Definition

Table 14-22. TBASE Field Descriptions

Bits

Name

Description

0–28

TBASE Transmit base. TBASE defines the starting location in the memory map for the TSEC TxBDs. This field

must be 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select how

many BDs to allocate for the transmit packets. The user must initialize TBASE before enabling the

TSEC transmit function.

29–31

—

Reserved

2 3 4

R PAD/CRC W I

TC DEF TO1 HFE/LC RL

OSTBDLEN

Reset

0000_1000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_42B0; TSEC2:0x2_52B0

Figure 14-25. OSTBD Register Definition

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