MPC8540 datasheet(665/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-39

Table 14-23 describes the fields of the OSTBD register.

Table 14-23. OSTBD Field Descriptions

Bits

Name

Description

Ready. Written by TSEC and user.

0 The data buffer associated with this BD is not ready for transmission. The user is free to

manipulate this BD or its associated data buffer. The TSEC clears this bit after the buffer is

transmitted or after an error condition is encountered.

1 The data buffer, which was prepared for transmission by the user, was not transmitted or is

currently being transmitted. No fields of this BD may be written by the user once this bit is set.

PAD/CRC

Padding and CRC attachment for short frames. (Valid only when MACCFG2[PAD/CRC] is cleared,

and MACCFG2[CRC EN] bit is cleared.) If MACCFG2[PAD/CRC] is set, pads are added to all

short frames; however, this bit is ignored.

0 Do not add PADs to short frames unless OSTBD[TC] is set.

1 Add PADs to short frames. PAD bytes are inserted until the length of the transmitted frame

equals 64 bytes. Unlike the MPC8260 which PADs up to MINFLR value, TSEC always PADs

up to the IEEE minimum frame length of 64 bytes.

Wrap. Written by user. This bit is ignored by TSEC.

Interrupt. Written by user.

0 No interrupt is generated after this buffer is serviced.

1 IEVENT[TXF] is set after this buffer is serviced. This bit can cause an interrupt if

IMASK[TXFEN] is enabled.

Last in Frame. The OSTBD is always the last in the frame, so L is always set. (Hardwired to a

value of 1.)

Tx CRC. Written by user. (Valid only while it is set in the first BD and OSTBD[PAD/CRC] is cleared,

MACCFG2[PAD/CRC] is cleared, and MACCFG2[CRC EN] is cleared.) If MACCFG2[PAD/CRC]

is set or MACCFG2[CRC EN] is set, a CRC is added to all frames and this bit is ignored.

0 End transmission immediately after the last data byte, unless OSTBD[PAD/CRC] is set.

1 Transmit the CRC sequence after the last data byte.

DEF

Defer indication. Written by TSEC.

Hardware updates this bit after transmitting a frame if used as a ‘Defer indicator.’ Software/user

updates this bit while building a transmit buffer descriptor if used as a ‘Hardware Event indicator.’

0 This frame was not deferred.

1 This frame did not have a collision before it was sent but it was sent late because of deferring.

TO1

Transmit software ownership. This read/write bit may be utilized by software, as necessary. Its

state does not affect the hardware nor is it affected by the hardware.

HFE/LC

Huge frame enable (written by user)/Late collision (written by TSEC)

Huge frame enable. Written by user. Valid only while it is set in first BD and the MACCFG2[Huge

Frame] is cleared. If MACCFG2[Huge Frame] is set, this bit is ignored.

0 Truncate transmit frame if its length is greater than the MAC’s Maximum Frame Length register.

1 Do not truncate the transmit frame.

Late collision. Written by TSEC.

0 No late collision.

1 A collision occurred after 64 bytes are sent. The TSEC terminates the transmission and

updates LC.

Retransmission limit. Written by TSEC.

0 Transmission before maximum retry limit is hit.

1 The transmitter failed (max. retry limit + 1) attempts to successfully send a message due to

repeated collisions. The TSEC terminates the transmission and updates RL.

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