MPC8540 datasheet(669/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-43

14.5.3.4.4 Receive Interrupt Coalescing Configuration Register (RXIC)

The RXIC register enables and configures the operational parameters for interrupt coalescing

associated with received frames. Refer to Section 14.6.2.8.1, “Interrupt Coalescing,” for a

functional description of interrupt coalescing as additional details regarding the use of this register.

Figure 14-30 shows the RXIC register.

Table 14-18 describes the fields of the RXIC register.

ICEN

ICFCT

ICTT

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4310; TSEC2:0x2_5310

Figure 14-30. RXIC Register Definition

Table 14-28. RXIC Field Descriptions

Bits

Name

Description

ICEN

Interrupt coalescing enable

0 Interrupt coalescing is disabled. Interrupts are raised as they are received if the TSEC receive frame

interrupt is enabled (IMASK[RXFEN] is set).

1 Interrupt coalescing is enabled. If the TSEC receive frame interrupt is enabled (IMASK[RXFEN] is

set), an interrupt is raised when the threshold number of frames is reached (defined by

RXIC[ICFCT]) or when the threshold timer expires (defined by RXIC[ICTT]).

1–2

—

Reserved

3–10

ICFCT Interrupt coalescing frame count threshold. While interrupt coalescing is enabled (RXIC[ICEN] is set),

this value determines how many frames are received before raising an interrupt1. Valid values for this

field are from 1 to 255. A value of 0 is illegal. If set to 0, an interrupt can only be cleared by first clearing

RXIC[ICEN] and then clearing the IEVENT[RXF] bit.

Note that a value of 1 functionally defeats the advantages of interrupt coalescing since the frame

threshold is reached with each frame received.

1 Interrupts resulting from the Interrupt bit (I) of the buffer descriptor in question and enabled subject to the IMASK register

(IMASK[RXFEN] is set).

11–15

—

Reserved

16–31

ICTT

Interrupt coalescing timer threshold. While interrupt coalescing is enabled (RXIC[ICEN] is set), this

value determines the maximum amount of time after receiving a frame before raising an interrupt 1,

subject also to IMASK[RXFEN]. If frames have been received but the frame count threshold has not

been met, an interrupt is raised when the threshold timer expires. The threshold timer is reset once an

interrupt has been asserted. It begins counting once the interrupt is cleared and IEVENT[RXF] is set.

The threshold value is represented in units equal to 64 TSEC interface clocks. Valid values for this field

are from 1 to 65535. A value of 0 is illegal. If set to 0, an interrupt can only be cleared by first clearing

RXIC[ICEN] and then clearing the IEVENT[RXF] bit.

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