MPC8540 datasheet(672/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-46

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-32 describes the fields of the RBASE register.

14.5.3.5 MAC Functionality

This section describes the MAC registers and provides a brief overview of the functionality that

can be exercised through the use of these registers, particularly those that provide functionality not

explicitly required by the IEEE 802.3 standard. All of the MAC registers are 32 bits wide.

14.5.3.5.1 Configuring the MAC

MAC configuration registers 1 and 2 provide a way to configure the MAC in multiple ways:

•

Adjusting the preamble length—The length of the preamble can be adjusted from the

nominal seven bytes to some other (non-zero) value.

•

Varying pad/CRC combinations—Three pad/CRC combinations are provided to handle a

variety of system requirements. The most simple are frames that already have a valid FCS

field. In this case, the CRC is checked and reported via the transmit statistics vector

(TSV[51:0]). The other two options include appending a valid CRC, or padding and then

appending a valid CRC, resulting in a minimum frame of 64 octets. In addition to the

programmable register set, the pad/CRC behavior can be dynamically adjusted on a

per-packet basis.

14.5.3.5.2 Controlling CSMA/CD

The half-duplex register (HAFDUP) allows control over the carrier-sense multiple

access/collision detection (CSMA/CD) logic of the TSEC. Half-duplex is only supported for 10

Mbps and 100 Mbps operation. Following the completion of the packet transmission the part

begins timing the inter packet gap (IPG) as programmed in the back-to-back IPG configuration

28 29

RBASE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4404; TSEC2:0x2_5404

Figure 14-34. RBASE Register Definition

Table 14-32. RBASE Field Descriptions

Bits

Name

Description

0–28

RBASE Receive base. RBASE defines the starting location in the memory map for the TSEC RxBD.

29–31

—

Reserved. These bits must be set to zero, to cause the value of RBASE to be a multiple of eight.

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