MPC8540 datasheet(676/1302 Pages) FREESCALE

676 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-50

Freescale Semiconductor

Three-Speed Ethernet Controllers

Reset Rx Fun Reset receive function block. This bit is cleared by default.

0 Normal operation

1 Place the receive function block in reset. This block performs the receive frame protocol.

Reset Tx Fun Reset transmit function block. This bit is cleared by default.

0 Normal operation

1 Place the transmit function block in reset. This block performs the frame transmission

protocol.

16–22

—

Reserved

Loop Back

Loop back. This bit is cleared by default.

0 Normal operation

1 Loop back the MAC transmit outputs to the MAC receive inputs.

24–25

—

Reserved

Rx_Flow

Receive flow. This bit is cleared by default.

0 The receive MAC control ignores PAUSE flow control frames.

1 The receive MAC control detects and acts on PAUSE flow control frames.

Tx_Flow

Transmit flow. This bit is cleared by default.

0 The transmit MAC control may not send PAUSE flow control frames if requested by the

system.

1 The transmit MAC control may send PAUSE flow control frames if requested by the system.

Sync’d Rx EN Receive enable synchronized to the receive stream (Read-only)

0 Frame reception is not enabled.

1 Frame reception is enabled.

Rx_EN

Receive enable. This bit is cleared by default. If set, prior to clearing this bit, set

DMACTRL[GRS] then confirm subsequent occurrence of the graceful receive stop interrupt

(IEVENT[GRSC] is set).

0 The MAC may not receive frames from the PHY.

1 The MAC may receive frames from the PHY.

Sync’d Tx EN Transmit enable synchronized to the transmit stream (Read-only)

0 Frame transmission is not enabled.

1 Frame transmission is enabled.

Tx_EN

Transmit enable. This bit is cleared by default. If set, prior to clearing this bit, set

DMACTRL[GTS] then confirm subsequent occurrence of the graceful transmit stop interrupt

(IEVENT[GTSC] is set).

0 The MAC may not transmit frames from the system.

1 The MAC may transmit frames from the system.

Table 14-33. MACCFG1 Field Descriptions (continued)

Bits

Name

Description

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