MPC8540 datasheet(680/1302 Pages) FREESCALE

680 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-54

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.5.3.6.5 Maximum Frame Length Register (MAXFRM)

The MAXFRM register is written by the user. Figure 14-39 shows the MAXFRM register.

Table 14-37 describes the fields of the MAXFRM register.

14.5.3.6.6 MII Management Configuration Register (MIIMCFG)

The MIIMCFG register is written by the user. Figure 14-40 shows the MIIMCFG register.

20–25

—

Reserved

26–31 Collision Window This is a programmable field representing the slot time or collision window during which

collisions occur in properly configured networks. Because the collision window starts at the

beginning of transmission, the preamble and SFD are included. Its default of 0x37 (55d)

corresponds to the count of frame bytes at the end of the window.

015 16

R 0

0000

Maximum Frame

Reset

0000_0000_0000_0000_0000_0110_0000_0000

Offset

TSEC1:0x2_4510; TSEC2:0x2_5510

Figure 14-39. Maximum Frame Length Register Definition

Table 14-37. MAXFRM Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31

Maximum

Frame

By default this field is set to 0x0600 (1536d). It sets the maximum frame size in both the

transmit and receive directions. (Refer to MACCFG2[Huge Frame].)

28 29

Reset

Mgmt

000 000 000 00 0 0 000 000 000 000 0

Pre

0Mgmt

Clock

Select

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4520; TSEC2:0x2_5520

Figure 14-40. MII Management Configuration Register Definition

Table 14-36. HAFDUP Field Descriptions (continued)

Bits

Name

Description

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