MPC8540 datasheet(682/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-56

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-39 describes the fields of the MIIMCOM register.

14.5.3.6.8 MII Management Address Register (MIIMADD)

The MIIMADD register is written by the user. Figure 14-42 shows the MIIMADD register.

Table 14-40 describes the fields of the MIIMADD register.

Table 14-39. MIIMCOM Field Descriptions

Bits

Name

Description

0–29

—

Reserved

Scan

Cycle

Scan cycle. This bit is cleared by default.

0 Normal operation.

1 The MII management continuously performs read cycles. This is useful for polling a PHY register, for

example, monitoring link fails. Data is returned in register MIIMSTAT[PHY Status].

Read

Cycle

Read cycle. This bit is cleared by default but is not self-clearing once set.

0 Normal operation.

1 The MII management performs a single read cycle upon the transition of this bit from 0 to 1 using the

PHY address (at MIIMADD[PHY Address]) and the register address (at MIIMADD[Register Address]).

The 0 to 1 transition of this bit also causes the MIIMIND[BUSY] bit to be set. The read is complete

when the MIIMIND[BUSY] bit clears. Data is returned in register MIIMSTAT[PHY Status].

18 19

23 24

26 27

R 000

000000

0000000

000

PHY Address

000

Address

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4528; TSEC2:0x2_5528

Figure 14-42. MIIMADD Register Definition

Table 14-40. MIIMADD Field Descriptions

Bits

Name

Description

0–18

—

Reserved

19–23

PHY Address

This field represents the 5-bit PHY address field of management cycles. Up to 31 PHYs can

be addressed (0 is reserved).

24–26

—

Reserved

27–31

registers can be accessed. Its default value is 0x00.

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