MPC8540 datasheet(685/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-59

Table 14-44 describes the fields of the IFSTAT register.

14.5.3.6.13Station Address Register Part 1 (MACSTNADDR1)

The MACSTNADDR1 register is written by the user. Figure 14-47 shows the MACSTNADDR1

MACSTNADDR2 is byte-reversed from how it would appear in the DA field of a frame in

memory. For example, for a station address of 0x12345678ABCD, perform a write to

MACSTNADDR1 of 0xCDAB7856, and to MACSTNADDR2 of 0x34120000. When the user

reads MACSTNADDR1, 0xCDAB7856 is returned. A read of MACSTNADDR2 returns a value

of 0x34120000. Note, the I/G and U/L bits of the frame’s DA field is located at the LSBs of the

1st octet stored in MACSTNADDR2, where the I/G bit is bit 15, and the U/L bit is bit 14.

Table 14-44. IFSTAT Field Descriptions

Bits

Name

Description

0–21

—

Reserved

Excess Defer Excessive transmission defer. This bit latches high and is cleared when read. This bit is cleared by

default.

0 Normal operation

1 The MAC excessively defers a transmission.

23–27

—

Reserved

Link Fail

Link Fail. This bit indicates the status of signal detection.

0 The100X module has detected a “signal detect” for longer than 330 mS.

1 The100X module has detected a “signal detect” for less than 330 mS or not at all.

29–31

—

Reserved

15 16

23 24

Station Address, 6th Octet Station Address, 5th Octet Station Address, 4th Octet Station Address, 3rd Octet

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4540; TSEC2:0x2_5540

Figure 14-47. Station Address Part 1 Register Definition

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