MPC8540 datasheet(689/1302 Pages) FREESCALE

689 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-63

Table 14-50 describes the fields of the TR511 register.

14.5.3.7.5 Transmit and Receive 512- to 1023-Byte Frame Counter Register

(TR1K)

Figure 14-53 shows the TR1K register.

Table 14-51 describes the fields of the TR1K register.

14.5.3.7.6 Transmit and Receive 1024- to 1518-Byte Frame Counter Register

(TRMAX)

Figure 14-54 shows the TRMAX register.

Table 14-50. TR511 Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–31 TR511 Increments for each good or bad frame transmitted and received which is 256 to 511 bytes in length,

inclusive (excluding preamble and SFD but including FCS bytes)

R 0

0 0 0 000000

TR1K

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4690; TSEC2:0x2_5690

Figure 14-53. Transmit and Receive 512- to 1023-Byte Frame Register Definition

Table 14-51. TR1K Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–31 TR1K Increments for each good or bad frame transmitted and received which is 512 to 1023 bytes in length,

inclusive (excluding preamble and SFD but including FCS bytes)

R 0

0 0 0 000 000

TRMAX

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4694; TSEC2:0x2_5694

Figure 14-54. Transmit and Receive 1024- to 1518-Byte Frame Register Definition

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