MPC8540 datasheet(687/1302 Pages) FREESCALE

687 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-61

RMON MIB group 1, RMON MIB group 2, RMON MIB group 3, RMON MIB group 9, RMON

MIB 2, and the 802.3 Ethernet MIB.

The detection of one or more of these statistical events triggers the MSTAT module to update its

statistics counters. These counters are stored in internal data registers. The user may access the

internal data registers at any time. An interrupt can be generated upon any one counter’s rollover

condition via a carry interrupt output from the MSTAT. Each counter’s rollover condition can be

discreetly masked from causing an interrupt by internal masking registers. In addition, each

individual counter value may be reset on read access, or all counters may be simultaneously reset

by assertion of an external module input signal. Figure 14-49 shows the TR64 register.

14.5.3.7.1 Transmit and Receive 64-Byte Frame Counter Register (TR64)

Table 14-47 describes the fields of the TR64 register.

14.5.3.7.2 Transmit and Receive 65- to 127-Byte Frame Counter Register

(TR127)

Figure 14-50 shows the TR127 register.

R 0 0 0 00 000 00

TR64

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4680; TSEC2:0x2_5680

Figure 14-49. Transmit and Receive 64-Byte Frame Register Definition

Table 14-47. TR64 Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–31 TR64 Transmit and receive 64-byte frame counter—Increment for each good or bad frame transmitted and

received which is 64 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes)

R 0

00000000

TR127

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4684; TSEC2:0x2_5684

Figure 14-50. Transmit and Receive 65- to 127-Byte Frame Register Definition

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