MPC8540 datasheet(691/1302 Pages) FREESCALE

691 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-65

Table 14-54 describes the fields of the RBYT register.

14.5.3.7.9 Receive Packet Counter Register (RPKT)

Figure 14-57 shows the RPKT register.

Table 14-55 describes the fields of the RPKT register.

14.5.3.7.10Receive FCS Error Counter Register (RFCS)

Figure 14-58 shows the RFCS register.

Table 14-54. RBYT Field Descriptions

Bits Name

Description

0—

Reserved

1–31 RBYT Receive byte counter. Increments by the byte count of frames received, including those in bad packets,

excluding preamble and SFD but including FCS bytes.

R 0

0 00000000

RPKT

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46A0; TSEC2:0x2_56A0

Figure 14-57. Receive Packet Counter Register Definition

Table 14-55. RPKT Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–31 RPKT Receive packet counter. Increments for each frame received packet (including bad packets, all unicast,

broadcast, and multicast packets).

015 16

R 0

000

00 0

RFCS

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46A4; TSEC2:0x2_56A4

Figure 14-58. Receive FCS Error Counter Register Definition

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