MPC8540 datasheet(693/1302 Pages) FREESCALE

693 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-67

Table 14-58 describes the fields of the RBCA register.

14.5.3.7.13Receive Control Frame Packet Counter Register (RXCF)

Figure 14-61 shows the RXCF register.

Table 14-59 describes the fields of the RXCF register.

14.5.3.7.14Receive Pause Frame Packet Counter Register (RXPF)

Figure 14-62 shows the RXPF register.

Table 14-58. RBCA Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–31 RBCA Receive broadcast packet counter. Increments for each broadcast good frame of lengths 64 to 1518

(non VLAN) or 1522 (VLAN), excluding multicast frames. Does not include range/length errors.

015 16

R 0 0 000 0000 0 0

0000

RXCF

Reset

0000_0000_0000_0000)0000_0000_0000_0000

Offset

TSEC1:0x2_46B0; TSEC2:0x2_56B0

Figure 14-61. Receive Control Frame Packet Counter Register Definition

Table 14-59. RXCF Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 RXCF Receive control frame packet counter. Increments for each MAC control frame received (both pause

control frames and control frames unsupported by IEEE).

015 16

R 0 0 0 0 000 000 0 0

0 0 0

RXPF

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46B4; TSEC2:0x2_56B4

Figure 14-62. Receive Pause Frame Packet Counter Register Definition

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