MPC8540 datasheet(697/1302 Pages) FREESCALE

697 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-71

Table 14-66 describes the fields of the RUND register.

14.5.3.7.21Receive Oversize Packet Counter Register (ROVR)

Figure 14-69 shows the ROVR register.

Table 14-67 describes the fields of the ROVR register.

14.5.3.7.22Receive Fragments Counter Register (RFRG)

Figure 14-70 shows the RFRG register.

Table 14-66. RUND Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 RUND Receive undersize packet counter. Increments each time a frame is received which is less than 64 bytes

in length and contains a valid FCS and were otherwise well formed. This count does not include range

length errors.

015 16

R 0

0 000000 00 0

ROVR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46D0; TSEC2:0x2_56D0

Figure 14-69. Receive Oversize Packet Counter Register Definition

Table 14-67. ROVR Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 ROVR Receive oversize packet counter. Increments each time a frame is received which exceeded 1518 (non

VLAN) or 1522 (VLAN) and contains a valid FCS and was otherwise well formed. This count does not

include range length errors.

15 16

R 0

0 0 0 0 0 0 0 0 0 0000

RFRG

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46D4; TSEC2:0x2_56D4

Figure 14-70. Receive Fragments Counter Register Definition

MPC8540 Datasheet(PDF) 697 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 697 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL