MPC8540 datasheet(699/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-73

Table 14-70 describes the fields of the RDRP register.

14.5.3.7.25Transmit Byte Counter Register (TBYT)

Figure 14-73 shows the TBYT register.

Table 14-71 describes the fields of the TBYT register.

14.5.3.7.26Transmit Packet Counter Register (TPKT)

Figure 14-74 shows the TPKT register.

Table 14-70. RDRP Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 RDRP Receive dropped packets counter. Increments for frames received which are streamed to system but

are later dropped due to lack of system resources.

TBYT

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46E0; TSEC2:0x2_56E0

Figure 14-73. Transmit Byte Counter Register Definition

Table 14-71. TBYT Field Descriptions

Bits Name

Description

0—

Reserved

1–31 TBYT Transmit byte counter. Increments by the number of bytes that were put on the wire including fragments

of frames that were involved with collisions. This count does not include preamble/SFD or jam bytes. This

counter does not count if the frame is truncated.

R 0

0 0 00 00 00 0

TPKT

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46E4; TSEC2:0x2_56E4

Figure 14-74. Transmit Packet Counter Register Definition

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