MPC8540 datasheet(703/1302 Pages) FREESCALE

703 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-77

Table 14-78 describes the fields of the TSCL register.

14.5.3.7.33Transmit Multiple Collision Packet Counter Register (TMCL)

Figure 14-81 shows the TMCL register.

Table 14-79 describes the fields of the TMCL register.

14.5.3.7.34Transmit Late Collision Packet Counter Register (TLCL)

Figure 14-82 shows the TLCL register.

Table 14-78. TSCL Field Descriptions

Bits

Name

Description

0–19

—

Reserved

20–31 TSCL Transmit single collision packet counter. Increments for each frame transmitted which experienced

exactly one collision during transmission.

19 20

R 0

0 0 0 0 0 0 0 0 0 00000

TMCL

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4700; TSEC2:0x2_5700

Figure 14-81. Transmit Multiple Collision Packet Counter Register Definition

Table 14-79. TMCL Field Descriptions

Bits

Name

Description

0–19

—

Reserved

20–31 TMCL Transmit multiple collision packet counter. Increments for each frame transmitted which experienced

2-15 collisions (including any late collisions) during transmission as defined using the

Half_Duplex[RETRANSMISSION MAXIMUM] field.

19 20

R 0

0 0 0 0 0 0 0 0 0 00000

TLCL

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4704; TSEC2:0x2_5704

Figure 14-82. Transmit Late Collision Packet Counter Register Definition

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