MPC8540 datasheet(705/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-79

Table 14-82 describes the fields of the TNCL register.

14.5.3.7.37Transmit Drop Frame Counter Register (TDRP)

Figure 14-85 shows the TDRP register.

Table 14-83 describes the fields of the TDRP register.

14.5.3.7.38Transmit Jabber Frame Counter Register (TJBR)

Figure 14-86 shows the TJBR register.

Table 14-82. TNCL Field Descriptions

Bits

Name

Description

0–19

—

Reserved

20–31 TNCL Transmit total collision counter. Increments by the number of collisions experienced during the

transmission of a frame as defined as the simultaneous presence of signals on the DO and RD circuits

(that is, transmitting and receiving at the same time). Note: This count does not include collisions that

result in an excessive collision condition.

015 16

R 0 0 0 00 00 00 0 0 0 0 0 0

TDRP

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4714; TSEC2:0x2_5714

Figure 14-85. Transmit Drop Frame Counter Register Definition

Table 14-83. TDRP Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31

TDRP

Transmit drop frame counter. Increments each time a memory error or an underrun has occurred.

R 0

0 000 000 00 0

TJBR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4718; TSEC2:0x2_5718

Figure 14-86. Transmit Jabber Frame Counter Register Definition

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