MPC8540 datasheet(702/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-76

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-76 describes the fields of the TDFR register.

14.5.3.7.31Transmit Excessive Deferral Packet Counter Register (TEDF)

Figure 14-79 shows the TEDF register.

Table 14-77 describes the fields of the TEDF register.

14.5.3.7.32Transmit Single Collision Packet Counter Register (TSCL)

Figure 14-80 shows the TSCL register.

Table 14-76. TDFR Field Descriptions

Bits

Name

Description

0–19

—

Reserved

20–31 TDFR Transmit deferral packet counter. Increments for each frame, which was deferred on its first

transmission attempt. This count does not include frames involved in collisions.

19 20

R 0

0 0 0 0 0 0 0 0 0 00000

TEDF

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46F8; TSEC2:0x2_56F8

Figure 14-79. Transmit Excessive Deferral Packet Counter Register Definition

Table 14-77. TEDF Field Descriptions

Bits

Name

Description

0–19

—

Reserved

20–31 TEDF Transmit excessive deferral packet counter. Increments for frames aborted which were deferred for an

excessive period of time (3036 byte times).

19 20

R 0

0 0 0 0 0 0 0 0 0 00000

TSCL

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46FC; TSEC2:0x2_56FC

Figure 14-80. Transmit Single Collision Packet Counter Register Definition

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