MPC8540 datasheet(704/1302 Pages) FREESCALE

704 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-78

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-80 describes the fields of the TLCL register.

14.5.3.7.35Transmit Excessive Collision Packet Counter Register (TXCL)

Figure 14-83 shows the TXCL register.

14.5.3.7.36Transmit Total Collision Counter Register (TNCL)

Figure 14-84 shows the TNCL register.

Table 14-80. TLCL Field Descriptions

Bits

Name

Description

0–19

—

Reserved

20–31 TLCL Transmit late collision packet counter. Increments for each frame transmitted which experienced a late

collision during a transmission attempt.

19 20

R 0

0 0 0 0 0 0 0 0 0 00000

TXCL

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4708; TSEC2:0x2_5708

Figure 14-83. Transmit Excessive Collision Packet Counter Register Definition

Table 14-81. TXCL Field Descriptions

Bits

Name

Description

0–19

—

Reserved

20–31 TXCL Transmit excessive collision packet counter. Increments for each frame that experienced 16 collisions

during transmission and was aborted.

19 20

R 0

0 0 0 0 0 0 0 0 0 00000

TNCL

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_470C; TSEC2:0x2_570C

Figure 14-84. Transmit Total Collision Counter Register Definition

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