MPC8540 datasheet(701/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-75

Table 14-74 describes the fields of the TBCA register.

14.5.3.7.29Transmit Pause Control Frame Counter Register (TXPF)

Figure 14-77 shows the TXPF register.

Table 14-75 describes the fields of the TXPF register.

14.5.3.7.30Transmit Deferral Packet Counter Register (TDFR)

Figure 14-78 shows the TDFR register.

Table 14-74. TBCA Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–31 TBCA Transmit broadcast packet counter. Increments for each broadcast frame transmitted (excluding

multicast frames).

015 16

R 0 0 000 000 00 0

0 0

TXPF

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46F0; TSEC2:0x2_56F0

Figure 14-77. Transmit Pause Control Frame Counter Register Definition

Table 14-75. TXPF Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 TXPF Transmit PAUSE frame packet counter. Increments each time a valid PAUSE MAC control frame is

transmitted.

19 20

R 0

0 0 0 0 0 0 0 0 0 00000

TDFR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46F4; TSEC2:0x2_56F4

Figure 14-78. Transmit Deferral Packet Counter Register Definition

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