MPC8540 datasheet(698/1302 Pages) FREESCALE

698 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-72

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-68 describes the fields of the RFRG register.

14.5.3.7.23Receive Jabber Counter Register (RJBR)

Figure 14-71 shows the RJBR register.

Table 14-69 describes the fields of the RJBR register.

14.5.3.7.24Receive Dropped Packet Counter Register (RDRP)

Figure 14-72 shows the RDRP register.

Table 14-68. RFRG Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 RFRG Receive fragments counter. Increments for each frame received which is less than 64 bytes in length

and contains an invalid FCS. This includes integral and non-integral lengths.

015 16

R 0 0 0 00 000 00 0

0 0

RJBR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46D8; TSEC2:0x2_56D8

Figure 14-71. Receive Jabber Counter Register Definition

Table 14-69. RJBR Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31

RJBR Receive jabber counter. Increments for frames received which exceed 1518 (non VLAN) or 1522 (VLAN)

bytes and contain an invalid FCS. This includes alignment errors.

015 16

R 0 0 0 0 0000 00 0

0 0

RDRP

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46DC; TSEC2:0x2_56DC

Figure 14-72. Receive Dropped Packet Counter Register Definition

MPC8540 Datasheet(PDF) 698 Page - Freescale Semiconductor, Inc

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