MPC8540 datasheet(695/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-69

Table 14-62 describes the fields of the RALN register.

14.5.3.7.17Receive Frame Length Error Counter Register (RFLR)

Figure 14-65 shows the RFLR register.

Table 14-63 describes the fields of the RFLR register.

14.5.3.7.18Receive Code Error Counter Register (RCDE)

Figure 14-66 shows the RCDE register.

Table 14-62. RALN Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 RALN Receive alignment error counter. Increments for each received frame from 64 to 1518 (non VLAN) or

1522 (VLAN) which contains an invalid FCS and is not an integral number of bytes.

015 16

R 0

0 00000000 00000

RFLR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46C0; TSEC2:0x2_56C0

Figure 14-65. Receive Frame Length Error Counter Register Definition

Table 14-63. RFLR Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 RFLR Receive frame length error counter. Increments for each frame received in which the 802.3 length field

did not match the number of data bytes actually received (46 –1500 bytes). The counter does not

increment if the length field is not a valid 802.3 length, such as an ethertype value.

015 16

R 0 0 00000000 0 0 0 0 0

RCDE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46C4; TSEC2:0x2_56C4

Figure 14-66. Receive Code Error Counter Register Definition

MPC8540 Datasheet(PDF) 695 Page - Freescale Semiconductor, Inc

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