MPC8540 datasheet(694/1302 Pages) FREESCALE

694 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-68

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-60 describes the fields of the RXPF register.

14.5.3.7.15Receive Unknown Opcode Packet Counter Register (RXUO)

Figure 14-63 shows the RXUO register.

Table 14-61 describes the fields of the RXUO register.

14.5.3.7.16Receive Alignment Error Counter Register (RALN)

Figure 14-64 shows the RALN register.

Table 14-60. RXPF Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 RXPF Receive PAUSE frame packet counter. Increments each time a valid PAUSE MAC control frame is

received.

015 16

R 0 0 0 0 000 00 0 0

0 0

RXUO

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46B8; TSEC2:0x2_56B8

Figure 14-63. Receive Unknown Opcode Packet Counter Register Definition

Table 14-61. RXUO Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 RXUO Receive unknown opcode counter. Increments each time a MAC control frame is received which

contains an opcode other than a PAUSE.

015 16

R 0 0 000 0000 0 0

0 0

RALN

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46BC; TSEC2:0x2_56BC

Figure 14-64. Receive Alignment Error Counter Register Definition

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