MPC8540 datasheet(692/1302 Pages) FREESCALE

692 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-66

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-56 describes the fields of the RFCS register.

14.5.3.7.11 Receive Multicast Packet Counter Register (RMCA)

Figure 14-59 shows the RMCA register.

Table 14-57 describes the fields of the RMCA register.

14.5.3.7.12Receive Broadcast Packet Counter Register (RBCA)

Figure 14-59 shows the RBCA register.

Table 14-56. RFCS Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 RFCS Receive FCS error counter. Increments for each frame received that has an integral 64 to 1518 length

and contains a frame check sequence error.

R 0

000

RMCA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46A8; TSEC2:0x2_56A8

Figure 14-59. Receive Multicast Packet Counter Register Definition

Table 14-57. RMCA Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–31 RMCA Receive multicast packet counter. Increments for each multicast good frame of lengths 64 to 1518 (non

VLAN) or 1522 (VLAN), excluding broadcast frames. This count does not include range/length errors.

R 000

000

RBCA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_46AC; TSEC2:0x2_56AC

Figure 14-60. Receive Broadcast Packet Counter Register Definition

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