MPC8540 datasheet(688/1302 Pages) FREESCALE

688 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-62

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-48 describes the fields of the TR127 register.

14.5.3.7.3 Transmit and Receive 128- to 255-Byte Frame Counter Register

(TR255)

Figure 14-51 shows the TR255 register.

Table 14-49 describes the fields of the TR255 register.

14.5.3.7.4 Transmit and Receive 256- to 511-Byte Frame Counter Register

(TR511)

Figure 14-52 shows the TR511 register.

Table 14-48. TR127 Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–31 TR127 Transmit and receive 65- to 127-byte frame counter—Increment for each good or bad frame transmitted

and received which is 65 to 127 bytes in length, inclusive (excluding preamble and SFD but including

FCS bytes)

09 10

R 0 0 0000 0000

TR255

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4688; TSEC2:0x2_5688

Figure 14-51. Transmit and Receive 128- to 255-Byte Frame Register Definition

Table 14-49. TR255 Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–31 TR255 Transmit and receive 128- to 255-byte frame counter—Increments for each good or bad frame

transmitted and received which is 128 to 255 bytes in length, inclusive (excluding preamble and SFD

but including FCS bytes)

09 10

R 0 0 00000000

TR511

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_468C; TSEC2:0x2_568C

Figure 14-52. Transmit and Receive 256- to 511-Byte Frame Register Definition

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