MPC8540 datasheet(690/1302 Pages) FREESCALE

690 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-64

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-52 describes the fields of the TRMAX register.

14.5.3.7.7 Transmit and Receive 1519- to 1522-Byte VLAN Frame Counter

Figure 14-55 shows the TRMGV register.

Table 14-53 describes the fields of the TRMGV register.

14.5.3.7.8 Receive Byte Counter Register (RBYT)

Figure 14-56 shows the RBYT register.

Table 14-52. TRMAX Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–31 TRMAX Increments for each good or bad frame transmitted and received which is 1024 to 1518 bytes in length,

inclusive (excluding preamble and SFD but including FCS bytes)

09 10

R 0 0 0 00 00 000

TRMGV

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4698; TSEC2:0x2_5698

Figure 14-55. Transmit and Receive 1519- to 1522-Byte VLAN Frame Register Definition

Table 14-53. TRMGV Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–31 TRMGV Increments for each good or bad frame transmitted and received which is 1519 to 1522 bytes in length,

inclusive (excluding preamble and SFD but including FCS bytes)

RBYT

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_469C; TSEC2:0x2_569C

Figure 14-56. Receive Byte Counter Register Definition

MPC8540 Datasheet(PDF) 690 Page - Freescale Semiconductor, Inc

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