MPC8540 datasheet(706/1302 Pages) FREESCALE

706 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-80

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-84 describes the fields of the TJBR register.

14.5.3.7.39Transmit FCS Error Counter Register (TFCS)

Figure 14-87 shows the TFCS register.

Table 14-85 describes the fields of the TFCS register.

14.5.3.7.40Transmit Control Frame Counter Register (TXCF)

Figure 14-88 shows the TXCF register.

Table 14-84. TJBR Field Descriptions

Bits

Name

Description

0–19

—

Reserved

20–31 TJBR Transmit jabber frame counter. Increments for each oversized transmitted frame with an incorrect FCS

value.

R 0

0 00000000 0000

TFCS

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_471C; TSEC2:0x2_571C

Figure 14-87. Transmit FCS Error Counter Register Definition

Table 14-85. TFCS Field Descriptions

Bits

Name

Description

0–19

—

Reserved

20–31

TFCS

Transmit FCS error counter. Increments for every valid sized packet with an incorrect FCS value.

19 20

R 0 0 0 0000 000 0

0 0

TXCF

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4720; TSEC2:0x2_5720

Figure 14-88. Transmit Control Frame Counter Register Definition

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