MPC8540 datasheet(683/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-57

14.5.3.6.9 MII Management Control Register (MIIMCON)

The MIIMCON register is written by the user. Figure 14-43 shows the MIIMCON register.

Table 14-41 describes the fields of the MIIMCON register.

14.5.3.6.10MII Management Status Register (MIIMSTAT)

The MIIMSTAT, shown in Figure 14-44, is read-only by the user.

Table 14-42 describes the fields of the MIIMSTAT register.

015 16

R 0

000

PHY Control

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_452C; TSEC2:0x2_552C

Figure 14-43. MII Management Control Register Definition

Table 14-41. MIIMCON Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31

PHY

Control

If written, an MII Mgmt write cycle is performed using this 16-bit data, the pre-configured PHY

address (at MIIMADD[PHY Address]) and the register address (at MIIMADD[Register Address]).

Its default value is 0x0000.

015 16

R 0

000

PHY Status

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4530; TSEC2:0x2_5530

Figure 14-44. MIIMSTAT Register Definition

Table 14-42. MIIMSTAT Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31

PHY Status

Following an MII Mgmt read cycle, the 16-bit data can be read from this location. Its default value

is 0x0000.

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