MPC8540 datasheet(681/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-55

Table 14-38 describes the fields of the MIIMCFG register.

14.5.3.6.7 MII Management Command Register (MIIMCOM)

The MIIMCOM register is written by the user. Figure 14-41 shows the MIIMCOM register.

Table 14-38. MIIMCFG Field Descriptions

Bits

Name

Description

Reset Mgmt Reset management. This bit is cleared by default.

0 Allow the MII Mgmt to perform management read/write cycles if requested.

1 Reset the MII Mgmt.

1–26

—

Reserved

No Pre

Preamble suppress. This bit is cleared by default.

0 The MII Mgmt performs management read/write cycles with 32 clocks of preamble.

1 The MII Mgmt suppresses preamble generation and reduces the management cycle from 64

clocks to 32 clocks. This is in accordance with IEEE 802.3/22.2.4.4.2.

—

Reserved

29–31

Mgmt Clock

Select

This field determines the clock frequency of the Mgmt Clock (EC_MDC). Its default value is 000.

The source clock frequency is equal to the core complex bus clock divided first by eight and then

futher divided by the following value:

000 Source clock divided by 4

001 Source clock divided by 4

010 Source clock divided by 6

011 Source clock divided by 8

100 Source clock divided by 10

101 Source clock divided by 14

110 Source clock divided by 20

111 Source clock divided by 28

R 0

000000 00000 0 00000000 00000000

0 Scan

Cycle

Read

Cycle

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4524; TSEC2:0x2_5524

Figure 14-41. MIIMCOM Register Definition

MPC8540 Datasheet(PDF) 681 Page - Freescale Semiconductor, Inc

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