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MPC8540 Datasheet(PDF) 678 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 678 Page - Freescale Semiconductor, Inc |
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678 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 14-52 Freescale Semiconductor Three-Speed Ethernet Controllers 14.5.3.6.3 Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG) The IPGIFG register is written by the user. Figure 14-37 shows the IPGIFG register. Table 14-35 describes the fields of the IPGIFG register. 0 1 7 8 9 15 16 23 24 25 31 R 0 Non-Back-to-Back Inter-Packet-Gap, Part 1 0 Non-Back-to-Back Inter-Packet-Gap, Part 2 Minimum IFG Enforcement 0 Back-to-Back Inter-Packet-Gap W Reset 0100_0000_0110_0000_0101_0000_0110_0000 Offset TSEC1:0x2_4508; TSEC2:0x2_5508 Figure 14-37. IPGIFG Register Definition Table 14-35. IPGIFG Field Descriptions Bits Name Description 0— Reserved 1–7 Non-Back-to-Back Inter-Packet-Gap, Part 1 Programmable field representing the optional carrier Sense window referenced in IEEE 802.3/4.2.3.2.1 ‘carrier deference’. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision; thus, ensuring fair access to medium. Its range of values is 0x00 to IPGR2. Its default is 0x40 (64d) which follows the two-thirds/one-third guideline. 8— Reserved 9–15 Non-Back-to-Back Inter-Packet-Gap, Part 2 Programmable field representing the non-back-to-back inter-packet-gap in bits. Its default is 0x60 (96d), which represents the minimum IPG of 96 bits. 16–23 Minimum IFG Enforcement Programmable field representing the minimum number of bits of IFG to enforce between frames. A frame is dropped whose IFG is less than that programmed. The default setting of 0x50 (80d) represents half of the nominal minimum IFG which is 160 bits. 24 — Reserved 25–31 Back-to-Back Inter-Packet-Gap Programmable field representing the IPG between back-to-back packets. This is the IPG parameter used exclusively in full-duplex mode and in half-duplex mode if two transmit packets are sent back-to-back. Set this field to the number of bits of IPG desired. The default setting of 0x60 (96d) represents the minimum IPG of 96 bits. |
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