MPC8540 datasheet(675/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-49

Yet another parameter that can be modified through the MII registers is the length of the MII

management interface preamble. After establishing that a PHY supports preamble suppression, the

host may so configure the TSEC. While enabled, the length of MII management frames are

reduced from 64 clocks to 32 clocks. This effectively doubles the efficiency of the interface.

14.5.3.6 MAC Registers

The following are the MAC registers.

14.5.3.6.1 MAC Configuration Register 1 (MACCFG1)

The MACCFG1 register is written by the user. Figure 14-35 shows the MACCFG1 register.

Table 14-33 describes the fields of the MACCFG1 register.

Soft_Reset

00 00 0 0

0 0

Reset

Rx MC

Reset

Tx MC

Reset

Rx Fun

Reset

Tx Fun

Reset

0000_0000_0000_0000

24 25

00 00 0 0

Loop Back

Rx_Flow Tx_Flow

Sync’d Rx EN

Rx_EN

Sync’d Tx EN

Tx_EN

Reset

0000_0000_0000_0000

Offset

TSEC1:0x2_4500; TSEC2:0x2_5500

Figure 14-35. MACCFG1 Register Definition

Table 14-33. MACCFG1 Field Descriptions

Bits

Name

Description

Soft_Reset

Soft reset. This bit is cleared by default. See Section 14.6.2.2, “Soft Reset and Reconfiguring

Procedure,” for more information on setting this bit.

0 Normal operation

1 Place all modules within the MAC in reset.

1–11

—

Reserved

Reset Rx MC Reset receive MAC control block. This bit is cleared by default.

0 Normal operation

1 Place the receive MAC control block in reset. This block detects control frames and contains

the pause timers.

Reset Tx MC Reset transmit MAC control block. This bit is cleared by default.

0 Normal operation

1 Place the PETMC transmit MAC control block in reset. This block multiplexes data and

control frame transfers. It also responds to XOFF PAUSE control frames.

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