MPC8540 datasheet(677/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-51

14.5.3.6.2 MAC Configuration Register 2 (MACCFG2)

The MACCFG2 register is written by the user. Figure 14-36 shows the MACCFG2 register.

Table 14-34 describes the fields of the MACCFG2 register.

15 16

19 20 2122 2324 25

R 0 0 000 000 000 000 0 0 Preamble

Length

I/F

Mode

00 Huge

Frame

Length

check

0 PAD/

CRC

Full

Duplex

Reset

0000_0000_0000_0000_0111_0000_0000_0000

Offset

TSEC1:0x2_4504; TSEC2:0x2_5504

Figure 14-36. MACCFG2 Register Definition

Table 14-34. MACCFG2 Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–19

Preamble

Length

Determines the length in bytes of the preamble field of the packet. Its default is 0x7. A

preamble length of 0 is not supported.

20–21

—

Reserved

22–23

I/F Mode

Determines the type of interface to which the MAC is connected. Its default is 00.

00 Reserved

01 Nibble mode (MII)

10 Byte mode (GMII/TBI)

11 Reserved

24–25

—

Reserved

Huge Frame

Huge frame enable. Cleared by default.

0 Limit the length of frames to the MAXIMUM FRAME LENGTH value.

1 Frames longer than the MAXIMUM FRAME LENGTH may be transmitted and received.

Length check

Length check. This bit is cleared by default.

0 No length field checking is performed.

1 The MAC checks the frame’s length field to ensure it matches the actual data field length.

—

Reserved

PAD/CRC

Pad and append CRC. This bit is cleared by default.

0 Frames presented to the MAC have a valid length and contain a CRC.

1 The MAC pads all transmitted short frames and appends a CRC to every frame regardless

of padding requirement.

CRC EN

CRC enable. If the configuration bit PAD/CRC or the per-packet PAD/CRC bit is set, CRC EN

is ignored. This bit is cleared by default.

0 Frames presented to the MAC have a valid length and contain a valid CRC.

1 The MAC appends a CRC on all frames. Clear this bit if frames presented to the MAC have

a valid length and contain a valid CRC.

Full Duplex

Full duplex configure. This bit is cleared by default.

0 The MAC to operate in half-duplex mode only.

1 The MAC operates in full-duplex mode.

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