MPC8540 datasheet(668/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-42

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-26 describes the fields of the RSTAT register.

14.5.3.4.3 RxBD Data Length Register (RBDLEN)

RBDLEN is a DMA register that contains the number of bytes remaining in the current receive

buffer. Figure 14-29 shows the RBDLEN register.

Table 14-27 describes the fields of the RBDLEN register.

789

R0 00 00000

QHLT

000000 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4304; TSEC2:0x2_5304

Figure 14-28. RSTAT Register Definition

Table 14-26. RSTAT Field Descriptions

Bits

Name

Description

0–7

—

Reserved

QHLT

RxBD queue is halted. When IEVENT[BSY] or IEVENT[EBERR] is set during reception of a packet,

RSTAT[QHLT] is also set. In order to begin receiving packets again, the user must clear RSTAT[QHLT].

This bit is set whenever the TSEC reads an RxBD with its Empty field cleared or encounters a system

bus error while processing an RX packet. It is a hardware-initiated stop indication (DMA_CTRL[GRS]

being set by the user does not cause this bit to be set.). The current frame and all other frames directed

to the halted queue are discarded. A write with a value of 1 re-enables the queue for receiving.

0 RxBD queue is enabled for Ethernet reception. (That is, it is not halted.)

1 All Ethernet controller receive activity to RxBD queue is halted.

9–31

—

Reserved

015 16

R 00000000000000

RBDLEN

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_430C; TSEC2:0x2_530C

Figure 14-29. RBDLEN Register Definition

Table 14-27. RBDLEN Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31

RBDLEN The RBDLEN is internally written by the DMA module. If RBDLEN is cleared, all activity in the

receive channel stops.

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