MPC8540 datasheet(670/1302 Pages) FREESCALE

670 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-44

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.5.3.4.5 Current Receive Buffer Descriptor Pointer Register (CRBPTR)

CRBPTR contains the address of the receive buffer descriptor either currently being processed, or

processed most recently. Figure 14-31 shows the CRBPTR register.

Table 14-29 describes the fields of the CRBPTR register.

14.5.3.4.6 Maximum Receive Buffer Length Register (MRBLR)

The MRBL register is written by the user. It informs the TSEC how much space is in the receive

buffer pointed to by the RxBD. Figure 14-32 shows the MRBLR.

28 29

CRBPTR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_4324; TSEC2:0x2_5324

Figure 14-31. CRBPTR Register Definition

Table 14-29. CRBPTR Field Descriptions

Bits

Name

Description

0–28

CRBPTR

The CRBPTR register is internally written by the DMA module. The value of this field increments by

one (causing the register value to increment by eight) each time a descriptor is read from memory.

29–31

—

Reserved

015 16

25 26

R 0

MRBL

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4340; TSEC2:0x2_5340

Figure 14-32. MRBL Register Definition

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