MPC8540 datasheet(667/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-41

14.5.3.4.1 Receive Control Register (RCTRL)

RCTRL, shown in Figure 14-27, controls the operational mode of the receive block. It must be

written only after a system reset (at initialization) or if DMACTRL[GRS] is cleared.

Table 14-25 describes the fields of the RCTRL register.

14.5.3.4.2 Receive Status Register (RSTAT)

TSEC writes to RSTAT, shown in Figure 14-28, under the following conditions:

•

The receiver runs out of descriptors.

•

The receiver was halted because an error condition was encountered while receiving a

frame.

Software must clear the QHLT bit to take the TSEC receiver function out of a halt state.

30 31

R 0 000 000 000 000 00 0

0 000 000 000 0

BC_REJ PROM RSF

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4300; TSEC2:0x2_5300

Figure 14-27. RCTRL Register Definition

Table 14-25. RCTRL Field Descriptions

Bits

Name

Description

0–26

—

Reserved

BC_REJ

Broadcast frame reject. If this bit is set, frames with DA

(destination address) = FFFF_FFFF_FFFF are rejected unless RCTRL[PROM] is set. If both

BC_REJ and RCTRL[PROM] are set, then frames with broadcast DA are accepted and the M

(MISS) bit is set in the receive BD.

0 Broadcast frame reject is disabled.

1 Broadcast frame reject is enabled.

PROM

Promiscuous mode. When set, all frames except pause frames are accepted.

0 Promiscuous mode is disabled.

1 Promiscuous mode is enabled.

RSF

Receive short frame mode. When set, enables the reception of frames shorter than MINFLR

bytes. Note that in order for short frames to be received when RSF is set, a DA hit must occur.

When RSF is cleared, all frames shorter than MINFLR are automatically rejected.

0 Receive short fram mode is disabled.

1 Receive short frame mode is enabled.

30–31

—

Reserved

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