MPC8540 datasheet(663/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-37

Table 14-20 describes the fields of the CTBPTR register.

14.5.3.3.6 Transmit Buffer Descriptor Pointer Register (TBPTR)

TBPTR, shown in Figure 14-23, contains the low-order 32 bits of the next transmit buffer

descriptor address. TBPTR takes on the TBASE value when TBASE is written by software.

Although not necessary in most applications, the user can modify this register when the transmitter

has been gracefully stopped or halted, as indicated by IEVENT[GTSC] or TSTAT[THLT].

Table 14-21 describes the fields of the TBPTR register.

14.5.3.3.7 Transmit Descriptor Base Address Register (TBASE)

The TBASE register, shown in Figure 14-24, is written by the user with the TxBD base address.

The value must be divisible by eight for the 8-byte data buffer descriptors.

Table 14-20. CTBPTR Field Descriptions

Bits

Name

Description

0–28

CTBPTR The CTBPTR register is internally written by the DMA module. The value of this field increments by

one (causing the register value to increment by eight) each time a descriptor is read from memory.

29–31

—

Reserved

28 29

TBPTR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_4184; TSEC2:0x2_5184

Figure 14-23.

TBPTR Register Definition

Table 14-21. TBPTR Field Descriptions

Bits

Name

Description

0–28

TBPTR

The TBPTR register is internally written by the DMA module. The value of this field increments by one

(causing the register value to increment by eight) each time a descriptor is read from memory.

29–31

—

Reserved

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