MPC8540 datasheet(662/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-36

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-18 describes the fields of the TXIC register.

14.5.3.3.5 Current Transmit Buffer Descriptor Pointer Register (CTBPTR)

CTBPTR contains the address of the transmit buffer descriptor either currently being processed,

or processed most recently. Figure 14-22 shows the CTBPTR register.

Table 14-19. TXIC Field Descriptions

Bits

Name

Description

ICEN

Interrupt coalescing enable

0 Interrupt coalescing is disabled. Interrupts are raised as they are received if the TSEC transmit frame

interrupt is enabled (IMASK[TXFEN] is set).

1 Interrupt coalescing is enabled. If the TSEC transmit frame interrupt is enabled (IMASK[TXFEN] is

set), an interrupt is raised when the threshold number of frames is reached (defined by

TXIC[ICFCT]) or when the threshold timer expires (defined by TXIC[ICTT]).

1–2

—

Reserved

3–10

ICFCT

Interrupt coalescing frame count threshold. While interrupt coalescing is enabled (TXIC[ICEN] is set),

this value determines how many frames are transmitted before raising an interrupt1. Valid values for

this field are from 1 to 255. A value of 0 is illegal. If set to 0, an interrupt can only be cleared by first

clearing TXIC[ICEN] and then clearing the IEVENT[TXF] bit.

Note that a value of 1 functionally defeats the advantages of interrupt coalescing since the frame

threshold is reached with each frame transmitted.

1 Interrupts resulting from the Interrupt bit (I) of the buffer descriptor in question and enabled subject to the IMASK register

(IMASK[TXFEN] is set).

11–15

—

Reserved

16–31

ICTT

Interrupt coalescing timer threshold. While interrupt coalescing is enabled (TXIC[ICEN] is set), this

value determines the maximum amount of time after transmitting a frame before raising an interrupt 1,

subject also to IMASK[TXFEN]. If frames have been transmitted but the frame count threshold has not

been met, an interrupt is raised when the threshold timer expires. The threshold timer is reset once an

interrupt has been asserted. It begins counting once the interrupt is cleared and IEVENT[TXF] is set.

The threshold value is represented in units equal to 64 TSEC interface clocks. Valid values for this field

are from 1 to 65535. A value of 0 is illegal. If set to 0, an interrupt can only be cleared by first clearing

TXIC[ICEN] and then clearing the IEVENT[TXF] bit.

28 29

CTBPTR

000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4124; TSEC2:0x2_5124

Figure 14-22. CTBPTR Register Definition

MPC8540 Datasheet(PDF) 662 Page - Freescale Semiconductor, Inc

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