MPC8540 datasheet(661/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-35

14.5.3.3.3 TxBD Data Length Register (TBDLEN)

TBDLEN is a DMA register that contains the number of bytes remaining in the current transmit

buffer. Figure 14-20 shows the TBDLEN register.

Table 14-18 describes the fields of the TBDLEN register.

14.5.3.3.4 Transmit Interrupt Coalescing Configuration Register (TXIC)

TXIC, shown in Figure 14-21, enables and configures the operational parameters for interrupt

coalescing associated with transmitted frames. Refer to Section 14.6.2.8.1, “Interrupt

Coalescing,” for a functional description of interrupt coalescing.

015 16

R 000 000000 000000 0

TBDLEN

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_410C; TSEC2:0x2_510C

Figure 14-20. TBDLEN Register Definition

Table 14-18. TBDLEN Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31

TBDLEN

Internally written by the DMA module. The transmit channel remains active until TBDLEN is 0.

10 11

15 16

ICEN

ICFCT

000

ICTT

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4110; TSEC2:0x2_5110

Figure 14-21. TXIC Register Definition

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