MPC8540 datasheet(659/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-33

Table 14-15 describes the fields of the FIFO transmit starve shutoff register.

14.5.3.3 TSEC Transmit Control and Status Registers

This section describes the control and status registers that are used specifically for transmitting

Ethernet frames. All of the registers are 32 bits wide.

14.5.3.3.1 Transmit Control Register (TCTRL)

TCTRL, shown in Figure 14-18, is writable by the user to configure the transmit block.

Table 14-16 describes the fields of the TCTRL register.

22 23

R 00000000000000000000

000

FIFO_TX_STARVE_SHUTOFF

Reset

0000_0000_0000_0000_0000_0001_0000_0000

Offset

TSEC1:0x2_409C; TSEC2:0x2_509C

Figure 14-17. FIFO_TX_STARVE_SHUTOFF Register Definition

Table 14-15. FIFO_TX_STARVE_SHUTOFF Field Descriptions

Bits

Name

Description

0–22

—

Reserved

23–31

FIFO_TX_STARVE_

SHUTOFF

FIFO transmit starve shutoff. Indicates the value beyond which to exit the starve state.

The starve state turns off if the number of valid entries in the FIFO becomes greater

than or equal to the FIFO Tx starve shutoff register.

019

R 000 000 000 000 000 0 0 00 0

THDF

0 0 0 0 0 0 RFC_PAUSE

TFC_PAUSE

00 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4100; TSEC2:0x2_5100

Figure 14-18. TCTRL Register Definition

Table 14-16. TCTRL Field Descriptions

Bits

Name

Description

0–19

—

Reserved

THDF

Transmit half-duplex flow control. Written by user. This bit is not self-resetting.

0 Disable back pressure.

1 Back pressure is applied to media.

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