MPC8540 datasheet(656/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-30

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-11 describes the fields of the TBIPA register.

14.5.3.2 TSEC FIFO Control and Status Registers

The following registers allow the user to change some of the default settings in the FIFO that can

be used to optimize operation for performance or for safety. They must be set carefully in order to

avoid an underrun condition. Underrun is an error condition in which data is not retrieved from

external memory quickly enough, leaving the TX FIFO empty before the complete frame is

transmitted. Because different combinations of events, several of which are determined by the

user, can lead to underrun, the TSEC provides several FIFO registers that allow the user to select

the proper setting to be able to tune the system and obtain the maximum performance with minimal

chance of underrun. The principal causes for underrun in the TSEC are:

•

Misaligned data buffer addresses

•

Small data buffer sizes

•

Combinations of the above

It is recommended that the minimum size data buffers be 64 bytes and that data buffers be 64-byte

aligned. The user can deviate from these recommended values to try to increase performance or to

use less memory, but unless the default values of some of the FIFO registers are adjusted, the

probability of an underrun may also increase. The FIFO_TX_THR (default is 256 entries or 1

Kbytes) indicates the amount of data required to be in the FIFO before starting the transmission of

a frame. The FIFO_TX_STARVE (default is 128 entries or 512 bytes) is used to indicate that the

amount of data in the FIFO is so low that the risk of underrun is extremely high. The

FIFO_TX_STARVE_SHUTOFF (default is 256 entries or 1 Kbyte) contains the watermark level

to be used for exiting the starve state. These registers are intended to allow the user to make the

proper trade-off. If triggered, the starve mode, for instance, automatically raises the priority of

TSEC fetches from memory.

14.5.3.2.1 FIFO Pause Control Register (FIFO_PAUSE_CTRL)

FIFO_PAUSE_CTRL, shown in Figure 14-14, is writable by the user to configure the properties

of the TSEC FIFO.

Table 14-11. TBIPA Field Descriptions

Bits

Name

Description

0–26

—

Reserved

27–31

TBIPA TBI PHY address. This field is used to program the PHY address of the ten-bit interface’s MII

management bus. To access the TBI register the user must write the TBIPA value to the MIIMADD

[PHY Address] register located in the MAC register section. Refer to Section 14.5.3.6.8, “MII

Management Address Register (MIIMADD).”

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