MPC8540 datasheet(655/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-29

14.5.3.1.8 TBI Physical Address Register (TBIPA)

This TBIPA, shown in Figure 14-13, is writable by the user to assign a physical address to the TBI

for MII management configuration. The TBI registers are accessed at the offset of TBIPA. For

detailed descriptions of the TBI registers (the MII register set for the ten-bit interface) please refer

to Section 14.5.4, “Ten-Bit Interface (TBI).”

WWR

Write with response. This bit gives the user the assurance that a BD was updated in memory before it

receives an interrupt concerning a transmit or receive frame.

0 Do not wait for acknowledgement from system for BD writes before setting IEVENT bits.

1 Before setting IEVENT bits TXB, TXF, TXE, IE, XFUN, LC, CRL/XDA, RXB, RXF, the TSEC waits for

acknowledgement from system that the transmit or receive BD being updated was stored in memory.

WOP

Wait or poll. This bit, which is applicable only to the transmitter, provides the user the option for the TSEC

to periodically poll TxBD or to wait for software to tell TSEC to fetch a buffer descriptor. While operating

in the “Wait” mode, the TSEC allows two additional reads of a descriptor which is not ready before

entering a halt state. No interrupt is driven. (IEVENT[TXE] is clear.) To resume transmission, software

must clear TSTAT[THLT].

Note that if this bit is set, the user must ensure that all TxBDs involved with sending a frame have their

ready bits set before any transmission begins. Otherwise, TSEC behaves in a boundedly undefined

fashion.

A buffer descriptor is considered not ready when its TxBD[Ready] field is clear or its TxBD[Data Length]

field is zero. It is considered ready when both TxBD[Ready] is set and TxBD[Data Length] is non-zero.

In Wait mode (DMACTRL[WOP] is set) when TSEC is processing a frame and an intermediate TxBD’s

ready bit is cleared, TSEC does not halt, but instead continuously polls the same TxBD until the TxBD

becomes ready or an Ethernet interface error or a memory error is encountered. CxBD becomes ready,

TSEC reports the error in both the IEVENT register as well as the TxBD for Ethernet interface errors, or

the IEVENT[EBERR] for a memory error and sets the TSTAT[THLT] bit. Note that software must

eventually set all of its TxBDs for a frame, because TSEC continuously reads an intermediate TxBD until

it becomes ready if insufficient data has been read to surpass the FIFO Transmit Threshold

(FIFO_TX_THR) register value.

0 Poll TxBD every 512 clocks.

1 Do not poll, but wait for a write to TSTAT[THLT].

26 27

R 0000000

0000000

00000000

00000

TBIPA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4030; TSEC2:0x2_5030

Figure 14-13. TBIPA Register Definition

Table 14-10. DMACTRL Field Descriptions (continued)

Bits

Name

Description

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