MPC8540 datasheet(649/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-23

14.5.3.1.2 Interrupt Mask Register (IMASK)

The interrupt mask register provides control over which possible interrupt events are allowed to

generate an actual interrupt. All implemented bits in this CSR are R/W. This register is cleared

upon a hardware reset. If the corresponding bits in both the IEVENT and IMASK registers are set,

an interrupt is generated. The interrupt signal can be cleared by clearing the corresponding

IEVENT bit.

Figure 14-7 shows the IMASK register.

XFUN

Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before the complete

frame was transmitted.

0 Transmit FIFO not underrun

1 Transmit FIFO underrun

RXB

Receive buffer. These bits indicate that a receive buffer descriptor was updated which had the I

(Interrupt) bit set in its status word and was not the last buffer descriptor of the frame.

0 Receive buffer descriptor not updated

1 Receiver buffer descriptor updated

17–22

—

Reserved

GRSC

Graceful receive stop complete. This interrupt is asserted if a graceful receive stop is completed. It

allows the user to know if the system has completed the stop and it is safe to write to receive registers

(status, control or configuration registers) that are used by the system during normal operation.

0 Graceful stop not completed

1 Graceful stop completed

RXF

Receive frame interrupt. The last receive buffer descriptor (RxBD) of a frame was updated. This occurs

only if the I (interrupt) bit in the buffer descriptor status word is set.

0 Frame not received

1 Frame received

25–31

—

Reserved

012

BREN RXCEN BSYEN EBERREN

MSROEN GTSCEN

BTEN

TXCEN TXEEN TXBEN TXFEN

LCEN

CRL/

XDAEN

XFUNEN

Reset

0000_0000_0000_0000

RXBEN

GRSCEN RXFEN

Reset

0000_0000_0000_0000

Offset

TSEC1:0x2_4014; TSEC2:0x2_5014

Figure 14-7. IMASK Register Definition

Table 14-4. IEVENT Field Descriptions (continued)

Bits

Name

Description

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