MPC8540 datasheet(643/1302 Pages) FREESCALE

643 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-17

0x2_4544

MACSTNADDR2—Station address register, part 2

R/W

0x0000_0000

14.5.3.6.14/14-60

0x2_4548–

0x2_467C

Reserved

0x0000_0000

—

TSEC1 RMON MIB Registers

TSEC1 Transmit and Receive Counters

0x2_4680

TR64—Transmit and receive 64-byte frame counter

R/W

0x0000_0000

14.5.3.7.1/14-61

0x2_4684

TR127—Transmit and receive 65- to 127-byte frame

counter register

R/W

0x0000_0000

14.5.3.7.2/14-61

0x2_4688

TR255—Transmit and receive 128- to 255-byte frame

counter register

R/W

0x0000_0000

14.5.3.7.3/14-62

0x2_468C

TR511—Transmit and receive 256- to 511-byte frame

counter register

R/W

0x0000_0000

14.5.3.7.4/14-62

0x2_4690

TR1K—Transmit and receive 512- to 1023-byte frame

counter register

R/W

0x0000_0000

14.5.3.7.5/14-63

0x2_4694

TRMAX—Transmit and receive 1024- to 1518-byte

frame counter register

R/W

0x0000_0000

14.5.3.7.6/14-63

0x2_4698

TRMGV—Transmit and receive 1519- to 1522-byte good

VLAN frame count register

R/W

0x0000_0000

14.5.3.7.7/14-64

TSEC1 Receive Counters

0x2_469C

RBYT—Receive byte counter register

R/W

0x0000_0000

14.5.3.7.8/14-64

0x2_46A0

RPKT—Receive packet counter register

R/W

0x0000_0000

14.5.3.7.9/14-65

0x2_46A4

RFCS—Receive FCS error counter register

R/W

0x0000_0000

14.5.3.7.10/14-65

0x2_46A8

RMCA—Receive multicast packet counter register

R/W

0x0000_0000

14.5.3.7.11/14-66

0x2_46AC

RBCA—Receive broadcast packet counter register

R/W

0x0000_0000

14.5.3.7.12/14-66

0x2_46B0

RXCF—Receive control frame packet counter register

R/W

0x0000_0000

14.5.3.7.13/14-67

0x2_46B4

RXPF—Receive PAUSE frame packet counter register

R/W

0x0000_0000

14.5.3.7.14/14-67

0x2_46B8

RXUO—Receive unknown OP code counter register

R/W

0x0000_0000

14.5.3.7.15/14-68

0x2_46BC

RALN—Receive alignment error counter register

R/W

0x0000_0000

14.5.3.7.16/14-68

0x2_46C0

RFLR—Receive frame length error counter register

R/W

0x0000_0000

14.5.3.7.17/14-69

0x2_46C4

RCDE—Receive code error counter register

R/W

0x0000_0000

14.5.3.7.18/14-69

0x2_46C8

RCSE—Receive carrier sense error counter register

R/W

0x0000_0000

14.5.3.7.19/14-70

0x2_46CC

RUND—Receive undersize packet counter register

R/W

0x0000_0000

14.5.3.7.20/14-70

0x2_46D0

ROVR—Receive oversize packet counter register

R/W

0x0000_0000

14.5.3.7.21/14-71

0x2_46D4

RFRG—Receive fragments counter register

R/W

0x0000_0000

14.5.3.7.22/14-71

Table 14-3. Module Memory Map (continued)

Offset

Name

Access1

Reset

Section/Page

MPC8540 Datasheet(PDF) 643 Page - Freescale Semiconductor, Inc

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