MPC8540 datasheet(641/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-15

0x2_4090–

0x2_4094

Reserved

0x0000_0000

—

0x2_4098

FIFO_TX_STARVE—FIFO transmit starve register

R/W

0x0000_0080

14.5.3.2.3/14-32

0x2_409C

FIFO_TX_STARVE_SHUTOFF—FIFO transmit starve

shutoff register

R/W

0x0000_0100

14.5.3.2.4/14-32

0x2_40A0–

0x2_40FC

Reserved

0x0000_0000

—

TSEC1 Transmit Control and Status Registers

0x2_4100

TCTRL—Transmit control register

R/W

0x0000_0000

14.5.3.3.1/14-33

0x2_4104

TSTAT—Transmit status register

R/W

0x0000_0000

14.5.3.3.2/14-34

0x2_4108

Reserved

0x0000_0000

—

0x2_410C

TBDLEN—TxBD data length register

0x0000_0000

14.5.3.3.3/14-35

0x2_4110

TXIC—Transmit interrupt coalescing configuration

R/W

0x0000_0000

14.5.3.3.4/14-35

0x2_4114–

0x2_4120

Reserved

0x0000_0000

—

0x2_4124

CTBPTR—Current TxBD pointer register

0x0000_0000

14.5.3.3.5/14-36

0x2_4128–

0x2_4180

Reserved

0x0000_0000

—

0x2_4184

TBPTR—TxBD pointer register

R/W

0x0000_0000

14.5.3.3.6/14-37

0x2_4188–

0x2_4200

Reserved

0x0000_0000

—

0x2_4204

TBASE—TxBD base address register

R/W

0x0000_0000

14.5.3.3.7/14-37

0x2_4208–

0x2_42AC

Reserved

0x0000_0000

—

0x2_42B0

OSTBD—Out-of-sequence TxBD register

R/W

0x0800_0000

14.5.3.3.8/14-38

0x2_42B4

OSTBDP—Out-of-sequence Tx data buffer pointer

R/W

0x0000_0000

14.5.3.3.9/14-40

0x2_42B8–

0x2_42FC

Reserved

0x0000_0000

—

TSEC1 Receive Control and Status Registers

0x2_4300

RCTRL—Receive control register

R/W

0x0000_0000

14.5.3.4.1/14-41

0x2_4304

RSTAT—Receive status register

R/W

0x0000_0000

14.5.3.4.2/14-41

0x2_4308

Reserved

0x0000_0000

—

0x2_430C

RBDLEN—RxBD data length register

0x0000_0000

14.5.3.4.3/14-42

Table 14-3. Module Memory Map (continued)

Offset

Name

Access1

Reset

Section/Page

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