MPC8540 datasheet(639/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-13

14.5 Memory Map/Register Definition

The TSEC uses a software model similar to that employed by the Fast Ethernet function supported

on the Freescale MPC8260 CPM FCC and in the FEC of the MPC860T.

The TSEC device is programmed by a combination of control/status registers (CSR) and buffer

descriptors. The CSRs are used for mode control, interrupts, and to access status information. The

descriptors are used to pass data buffers and related buffer status or frame information between the

hardware and software.

All accesses to and from the registers must be made with 32-bit accesses. There is no support for

accesses of sizes other than 32 bits.

This section of the document defines the memory map and describes the registers in detail. The

buffer descriptor is described in Section 14.6.3, “Buffer Descriptors.”

The ten-bit interface (TBI) module MII registers are also described in this section. The TBI

registers are defined like PHY registers and, as such, are accessed via the MII management

interface in the same way as the PHYs are accessed. For detailed descriptions of the TBI registers

(the MII register set for the ten-bit interface) please refer to Section 14.5.4, “Ten-Bit Interface

(TBI).”

14.5.1 Top-Level Module Memory Map

The TSEC implementation requires 4 Kbytes of memory-mapped space, of which more than 1

Kbyte is reserved for future expansion. The space is divided into the following sections:

•

General control/status registers

•

Transmit-specific control/status registers

•

Receive-specific control/status registers

•

MAC registers

•

Event/statistic counters held in the MIB block

•

Hash function registers

Table 14-2 defines the top-level memory map.

Table 14-2. Module Memory Map Summary

Address

Function

000–0FF

TSEC general control/status registers

100–2FF

TSEC transmit control/status registers

300–4FF

TSEC receive control/status registers

500–5FF

TSEC MAC registers

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