MPC8540 datasheet(916/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-94

Freescale Semiconductor

PCI/PCI-X Bus Interface

There is a rare situation where an internal access (originating from either the processor core, or

other I/O ports on the device) to the 256-byte PCI-X configuration header may be corrupted by

concurrent outbound PCI-X data transactions. The corruption does not occur if the PCI-X

configuration transactions and the outbound PCI-X data transactions are not concurrent. The

corruption does not occur with inbound PCI-X traffic. This is an issue for any system that mixes

internally generated PCI-X configuration transactions with outbound PCI-X data transactions.

There are two ways to avoid the situation:

1. Ensure that PCI-X configuration transactions are completed before starting PCI-X data

transactions.

2. Ensure that all PCI-X outbound data traffic is quiesced before attempting PCI-X

configuration transactions. The programmer must ensure all of the following:

— Non-configuration transactions to PCI-X from the processor core are quiesced.

— The core is not fetching instructions from PCI-X.

— DMA transactions to PCI-X are quiesced.

— RapidIO bridging transactions to PCI-X are quiesced.

As is the case for PCI configuration accesses, the bus master bit in the MPC8540’s PCI bus

command register must be set before an outbound configuration access is attempted. Figure 16-79

shows the PCI-X type 0 translation function performed on the contents of the PCI CFG_ADDR

Figure 16-79. PCI-X Type 0 Configuration Translation

Compare the PCI-X translation in Figure 16-79 with the PCI configuration translation shown in

Figure 16-66. Note that for PCI-X mode in addition to being used to generate the IDSEL signal,

the device number is repeated on AD[15:11].

0 1

7 8

15 16

20 21

23 24

29 30 31

Bus Number

000_0000

Reserved

Device Number

Function Number

3116 15

2 1

IDSEL–Only One Signal High

Contents of PCI CFG_ADDR Register

PCI_AD[31:0] Signals

During Address Phase

See Table 16-63

Device/Function/Register Number

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