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MPC8540 Datasheet(PDF) 917 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 917 Page - Freescale Semiconductor, Inc |
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917 / 1302 page ![]() Functional Description MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 16-95 For PCI-X type 0 configuration cycles, the MPC8540 translates the device number field of PCI CFG_ADDR into a unique IDSEL signal for up to 15 different devices. Each device connects its IDSEL input to one of the AD[31:17] signals. For PCI-X type 0 configuration cycles, the MPC8540 translates the device number to ADn as shown in Table 16-63. For PCI-X type 0 translations, the function number and register number fields are copied without modification onto PCI_AD[15:2] during the address phase. PCI_AD[1:0] are driven to 0b00 during the address phase for PCI-X type 0 configuration cycles. The MPC8540 implements address stepping on configuration cycles so that the target’s IDSEL, which is connected directly to one of the PCI_AD lines, reaches a stable value. This means that a valid address and command are driven on PCI_AD[31:0] and PCI_C/BE[3:0] four clocks before the assertion of PCI_FRAME. PCI-X configuration transactions include an attribute phase one clock cycle after the address phase. The the attribute for a configuration transaction is similar to the DWORD transaction attribute. For the configuration attribute, PCI_C/BE[3:0] provide the byte enables and AD[31:0] are driven as shown in Figure 16-80. Figure 16-80. AD[31:0] During PCI-X Configuration Attribute Phase Table 16-63. PCI-X Type 0 Configuration—Device Number to ADn Translation Device Number AD Signal Used for IDSEL Device Number AD Signal Used for IDSEL Binary Decimal Binary Decimal 0b0_0000 0 — 0b0_1001 9 AD25 0b0_0001 1 AD17 0b0_1010 10 AD26 0b0_0010 2 AD18 0b0_1011 11 AD27 0b0_0011 3 AD19 0b0_1100 12 AD28 0b0_0100 4 AD20 0b0_1101 13 AD29 0b0_0101 5 AD21 0b0_1110 14 AD30 0b0_0110 6 AD22 0b0_1111 15 AD31 0b0_0111 7 AD23 0b1_xxxx — — 0b0_1000 8 AD24 0b1_1111 1 1 A device number of all ones indicates a PCI-X special-cycle or interrupt-acknowledge transaction. 31 — 000 Tag Requester Bus Number 31 29 28 24 23 16 Requester Device Number Requester Function Number Secondary Bus Number 15 11 10 8 7 0 |
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