MPC8540 datasheet(921/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-99

When an outbound PCI-X read transaction has been split and the split completion transaction

indicates a master-abort or a target-abort, the split-completion error message (SCEM) data field

contains information for setting the received master-abort or received target-abort bit in the PCI

bus status register (bits 13 and 12, respectively). However, for misaligned reads (that is, reads not

aligned on a 64-bit boundary), the error is not reflected in the PCI bus status register. The error is

reported in the PCI error detection register (ERR_DR) at 0x0_8E00. The master-abort or

target-abort can be inferred from the error data capture register (ERR_DL). Drivers that require

this information can read the ERR_DR register rather than the PCI bus status register.

16.5 Initialization/Application Information

This section describes some tips for use of the PCI/X controller.

16.5.1 Power-On Reset Configuration Modes

The PCI/X block can power-on in three modes: host mode, agent mode and agent configuration

lock mode. Certain bits in the configuration registers are set differently according to the POR

(power-on reset) mode. Also, certain configuration bits have different implications when

compared with past Freescale Semiconductor parts and PCI implementations. Note that after reset,

the device cannot be switched from one mode to another.

The affected configuration bits are defined in Table 16-66.

Table 16-66. Affected Configuration Register Bits for POR

(offset)

Name

PCI bus

command

(0x04)

2Bus

master

Controls whether the device can master a transaction on the PCI/X bus. If cleared, the device

can not master a transaction. This bit is independent of host or agent mode.

Memory

space

Controls acknowledgement of inbound memory transactions. If cleared, all inbound memory

accesses (including accesses to PCSRBAR space) end in a master abort. This bit is

independent of host or agent mode.

PCI bus

function

(0x44)

ACL

Valid only in agent mode. Controls acknowledgement of inbound configuration accesses.

If set, all inbound configuration accesses are retried. If cleared, inbound configuration

accesses are acknowledged.

In host mode all inbound configuration accesses end in master aborts.

PAH

Determines whether the device is in agent or host mode. Zero indicates host mode.

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