MPC8540 datasheet(925/1302 Pages) FREESCALE

925 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-1

Chapter 17

RapidIO Interface

The RapidIO controller conforms to Revision 1.2 of the Parallel RapidIO Interconnect

Specification. This chapter describes the implementation of the parallel RapidIO controller.

17.1 Introduction

The RapidIO controller is partitioned into inbound and outbound blocks, and these blocks are

further partitioned into three implementation layers: physical, protocol, and logical. Note that

these implementation layers do not precisely correlate with the layers described in the Parallel

RapidIO Interconnect Specification. The physical and protocol layers primarily address the

portion of the Parallel RapidIO Interconnect Specification titled “Physical Layer 8/16 LP-EP.”

The logical layer refers primarily to the logical portions of the Parallel RapidIO Interconnect

Specification. The physical layer operates at the RapidIO interface applied frequency, and data is

sampled at twice this frequency. The protocol and logical layers operate at the device frequency.

17.1.1 Overview

A block diagram of The RapidIO controller is shown in Figure 17-1 and includes a RapidIO

interface and a system core interface; those signals are divided into several groups. These groups

include: the RapidIO request, response, ack done, and data transfer interfaces, the system core

request, response and data transfer interfaces, the register access interface, which is used to access

the programming model registers, the interrupt interface, the systems functions interface, and the

performance monitor interface.

MPC8540 Datasheet(PDF) 925 Page - Freescale Semiconductor, Inc