MPC8540 datasheet(929/1302 Pages) FREESCALE

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Introduction

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-5

•

A message-passing programming model

•

Default and configurable inbound ATMU window

•

Default outbound ATMU window

•

CRC-based error detection (CCITT-CRC16) as described in the 8/16 LP-EP physical

specification

•

256-byte data payloads

•

Packet pacing/retry capability

•

Only the small size transport information field (TT = 0b00)

•

Link validation, error recovery, training, and time-out support as required by the physical

layer specification

•

RapidIO error injection

17.1.3.2 Features Not Implemented

The following portions of the Parallel RapidIO Interconnect Specification are not supported:

•

Large size transport information field (TT = 0b01)

•

TOD-sync control symbols (these are treated as idle control symbols)

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Atomic swap or atomic test and swap transactions

17.1.4 RapidIO Modes of Operation

This section describes the RapidIO modes of operation.

17.1.4.1 Transmit Clock-Select Mode

The RapidIO transmit clock can be chosen from either an internal source or from the RapidIO

receive clock signal. The clock source is selected at power-on reset, as described in

Section 4.4.3.10, “RapidIO Transmit Clock Source,” and Section 4.4.4.2, “RapidIO Clocks.” Note

that the CCB clock is the clock signal for the rest of the RapidIO block.

17.1.4.2 CRC Checking Modes

RapidIO offers the modes for packet CRC checking shown in Table 17-2. Note that a read that

attempts to access an unmapped target causes the assertion of core_fault_in, which causes the core

to generate a machine check interrupt, unless it is disabled (by clearing HID1[RFXE]). If RFXE

is zero and this error occurs, PCR[CCE] must be set to ensure that an interrupt is generated. For

more information, see Section 6.10.2, “Hardware Implementation-Dependent Register 1 (HID1).”

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